1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
In recent years, with progress of digital technology, nonvolatile memories, in which a large volume of data can be stored at a high speed, have been developed.
As such nonvolatile memories, flush memories and ferroelectric memories are known.
Of these, flush memories have a floating gate buried in a gate insulating film of an insulated-gate field-effect transistor (IGFET), and accumulate, in this floating gate, charge representing information to be stored, thus storing the information. However, in the flash memory, tunnel current needs to be passed through the gate insulating film when information is written or deleted. Therefore, the flash memory has a disadvantage that a relatively high voltage is needed.
Meanwhile, ferroelectric memories are also called ferroelectric random access memories (FeRAMs), and store information by utilizing hysteresis characteristics of a ferroelectric film provided in a ferroelectric capacitor. The ferroelectric film is polarized according to a voltage applied between upper and lower electrodes of the capacitor, and retains spontaneous polarization even when the voltage is removed. When the polarization of the applied voltage is reversed, the spontaneous polarization is also reversed. Information is written to the ferroelectric film by use of the orientation of the spontaneous polarization associated with “1” or “0.” Voltage needed for this writing is lower than that for flash memories. Moreover, FeRAMs have an advantage that writing can be performed at a high speed compared to a case of flash memories.
The performance of a ferroelectric capacitor provided in an FeRAM greatly depends on a film quality of a ferroelectric film. Accordingly, in order to provide high-quality FeRAMs, many studies have been conducted for optimization of a method of depositing a ferroelectric film, the heat treatment of a ferroelectric film, and the like.
For example, Japanese Patent Application No. 2004-214569 (hereinafter referred to as Patent Document 1) proposes that a capacitor dielectric film be formed in a two-layer structure including first and second ferroelectric films. The deposition temperature of the first ferroelectric film is set at a temperature at which the first ferroelectric film is caused to have a crystallized structure exhibiting ferroelectricity. On the other hand, the deposition temperature of the second ferroelectric film is set lower than a temperature at which the second ferroelectric film is caused to have a crystallized structure exhibiting ferroelectricity. According to Patent Document 1, such a structure improves fatigue of a ferroelectric capacitor.
In Japanese Patent Application No. 2004-186517 (hereinafter referred to as Patent Document 2), in order to prevent the leakage current of a capacitor from increasing, first ferroelectric films and second ferroelectric films thicker than the first ferroelectric films are alternately stacked to form a capacitor dielectric film having a multilayer structure. In this case, the first ferroelectric films are subjected to rapid thermal anneal (RTA).
Furthermore, in Japanese Patent Application No. 2004-22702 (hereinafter referred to as Patent Document 3), a ferroelectric film, which is already crystallized at the time of deposition thereof, is formed by metal organic chemical vapor deposition (MOCVD). Then, heat treatment is performed on the ferroelectric film at a temperature higher than the deposition temperature thereof by 40° C. or more, thus improving the fatigue of a ferroelectric capacitor.
Indicators of the performance of a ferroelectric capacitor include a switching charge amount and imprint characteristics in addition to the above-described leakage current and fatigue. Ideally, it is preferable that all of the above be simultaneously improved.
However, the technologies described in Patent Documents 1 to 3 cannot simultaneously improve all of these characteristics, and cannot meet the demand for higher performance of FeRAMs.
For example, according to FIG. 3 of Patent Document 1, the number of polarization reversals, at which a decrease in a switching charge amount (Qsw) starts to be obvious, can be made one or two orders of magnitude larger than that in conventional cases. However, when the number of polarization reversals is approximately 106, the switching charge amount (Qsw) greatly decreases. The technology of Patent Document 1 cannot meet this demand for FeRAMs to have such a life that the switching charge amount does not decrease even when the number of polarization reversals becomes 1010 or more.
Moreover, with the technology of Patent Document 2, leakage current is indeed reduced by forming a capacitor dielectric film having a multilayer structure. However, there arises another problem in which a process is complicated when a multilayer structure having three or more layers is employed.
On the other hand, with the technology of Patent Document 3, the fatigue and imprint characteristics of a capacitor are improved. However, as shown in FIG. 10 of Patent Document 3, there is a problem that the switching charge amount decreases due to the annealing of a ferroelectric film.